Ece 734 Project Proposal Implementing and Optimizing a Direct Digital Frequency Synthesizer (ddfs) on Fpga Team Members
نویسندگان
چکیده
After doing a literature survey on the DFFS algorithms ([1] ~ [6]) proposed in recent years (after 2000), we select the algorithm presented in [1] to be implemented in our project. Compared with other algorithm we study in the literature survey, the selected algorithm is able to achieve highest clock frequency and spurious free dynamic range (SFDR) while requires a modest implementation complexity (but it is not optimal in terms of area and power).
منابع مشابه
Design and Simulation of a Modified 32-bit ROM-based Direct Digital Frequency Synthesizer on FPGA
This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum ope...
متن کاملAn optimized Direct Digital Frequency Synthesizer (DDFS)
An optimized Direct Digital Frequency Synthesizer (DDFS) design in terms of reduced ROM, high throughput and speed is designed in this paper. DDFS is designed with 200 MHz reference clock frequency and 32 bit FTW for the generation of sine and cosine signal with 16 bit output frequency having frequency resolution of 0.0466 Hz and Phase resolution of 0.0055°. DDFS design is simulated using VHDL ...
متن کاملHigh-SFDR and Multiplierless Direct Digital Frequency Synthesizer
This paper presents a hybrid COordinate Rotation DIgital Computer (CORDIC) algorithm for designs and implementations of the direct digital frequency synthesizer (DDFS). The proposed multiplier-less architecture with small ROM ( 4 16× -bit) and pipelined data path provides a spurious free dynamic range (SFDR) of more than 84.4 dBc. A SoC (System on Chip) has been designed by m . μ 18 0 1P6M CMOS...
متن کاملDirect Digital Frequency Synthesizer with CORDIC Algorithm and Taylor Series Approximation for Digital Receivers
In this document we are presenting a new approach to design an optimised Direct Digital Frequency Synthesizer (DDFS) for complex demodulation used in digital receivers. For that, we suggest an adaptation of the phase to sine converter by combining the two following techniques: 1) an optimized COordinate Rotation DIgital Computer (CORDIC) algorithm 2) the principle of Taylor series approximation...
متن کامل